Digital to analog converters (DACs) are utilized in a wide variety of applications (e.g., transmit DAC, envelope tracking DAC, and wireless local area network (WLAN) DAC). DACs can be susceptible to various types of errors including, but not limited to, errors related to current or voltage source mismatches, gain and offset errors, as well as errors caused by external signal paths. To achieve improved performance in the areas of signal-to-noise and distortion ratio (SNDR), total harmonic distortion (THD), and spurious free dynamic range (SFDR), self-calibration techniques are utilized to calibrate the output provided by a DAC.
One self-calibration technique includes a binary weighted configuration. For example, a P-type metal oxide semiconductor (PMOS) calDAC may be implemented in a binary weighted configuration to achieve improved performance of DACs. Each input digital bit of the binary weighted configuration controls a particular amount of analog binary weight, which is added/subtracted to/from an output of the binary weighted configuration. However, memory of the PMOS calDAC is implemented in a high voltage domain (e.g., VDD of 1.8V) and the memory occupies a large space of the calDAC (e.g., about fifty percent (50%) of the PMOS calDAC area). On the other hand, memory can be placed in a low voltage domain to reduce its area, but the PMOS calDAC in this case includes bulky level shifters that occupy an increased amount of chip area.